1. Field of the Invention
The present invention is related to an overlay target, and more particularly, to an overlay target for optically measuring overlay alignment of layers formed on a semiconductor wafer.
2. Description of the Prior Art
In a variety of manufacturing and production settings, there is a need to control alignment between various layers or within particular layers of a given sample. For example, in the context of semiconductor processing, semiconductor-based devices may be produced by fabricating a series of layers on a substrate, some or all of the layers including various structures. The relative position of the structures both within a single layer and with respect to structures in other layers is critical to the performance of the devices. The misalignment between various structures is known as overlay error.
The measurement of overlay error between successive patterned layers on a wafer is one of the most critical process control techniques used in the manufacturing of integrated circuits and devices. Overlay accuracy generally pertains to the determination of how accurately a first patterned layer aligns with respect to a second patterned layer disposed above or below and to the determination of how accurately a first pattern aligns with respect to a second pattern disposed on the same layer. Presently, overlay measurements are performed via test patterns that are printed together with layers of the wafer. However, there are some shortcomings of conventional solutions such as asymmetry of patterned line profile that may bring to measurement error due to the inconsistent in x/y overlay direction measurement.